1. Field of the Invention
The present invention relates to alternating-current (AC) discharge plasma display devices and drive methods therefor.
2. Description of the Related Background Art
Plasma display devices including plasma display panels (in the below, referred also to as PDPs) serving as display panels generally have many advantages, e.g., thin-and-large-screen display with relative ease, wider viewing angle, and faster response speed. With such various advantages, the PDPs have recently become popular for use as flat displays of wall televisions, public display boards, and others. The PDPs are classified into two types of direct-current (DC) discharge PDPs and AC discharge PDPs according to their operation mode. The DC-type PDPs operate in response to direct-current discharge between electrodes, which are exposed to the discharge space filled with discharge gas. The AC-type PDPs operate under the conditions of AC discharge with electrodes not directly exposed to discharge gas with a dielectric layer therearound. With the DC-type PDPs, the discharge continues during voltage application, and with the AC-type PDPs, the discharge is sustained by reversing the voltage polarity. The AC-type PDPs are varying in the number of electrodes in a cell, i.e., two or three.
Described below is the structure and drive method of a conventional three-electrode AC-type plasma display device. FIG. 5 is a perspective view showing a display cell of the conventional AC-type plasma display device. FIG. 1 is a block diagram showing the conventional AC-type plasma display device. FIG. 2 is a circuit diagram showing a scan driver and a scan pulse driver of FIG. 1. FIG. 3 is a circuit diagram showing a sustain driver of FIG. 1. FIG. 4 is a circuit diagram showing a data driver of FIG. 1.
As shown in FIG. 1, the plasma display device is provided with a display panel 1, and a driving circuit therefor. The display panel 1 includes a plurality of display cells in a matrix.
By referring to FIG. 5, the display panel 1 is provided with two insulation substrates 101 and 102, both of which are made of glass. The insulation substrate 101 serves as a back substrate, and the insulation substrate 102 as a front substrate. The surface of the insulation substrate 102 facing the insulation substrate 101 carries transparent scanning electrodes 103 and transparent sustain electrodes 104, all of which are extending along the horizontal direction of the panel, i.e., lateral direction. In such a manner as to overlay on the scanning electrodes 103 and the sustain electrodes 104, trace electrodes 105 and 106 are provided. The trace electrodes 105 and 106 are made of metal, for example, and provided for the purpose of reducing the electrode resistance in value between the electrodes and an external drive. The scan electrodes 103 and the sustain electrodes 104 are covered by a dielectric layer 112, and the dielectric layer 112 is protected from discharge by a protection layer 114 made of magnesium oxide or others.
The surface of the insulation substrate 101 facing the insulation substrate 102 carries a data electrode 107. The data electrode 107 is placed orthogonal to the scan electrodes 103 and the sustain electrodes 104 viewed from the direction perpendicular to the surface of the insulation electrode 101, i.e., viewed from the top. The data electrode 107 thus extends along the perpendicular direction of the panel, i.e., longitudinal direction. A partition wall 109 is also provided to partition the display cell in the horizontal direction. A dielectric layer 113 covers the data electrode 107, and on the surface of the dielectric layer 113 and the side surfaces of the partition wall 109, a fluorescent layer 111 is formed. The fluorescent layer 111 is the one converting ultraviolet light into visible light 110 through discharge of discharge gas. By the partition wall 109, a discharge gas space 108 is reserved between the insulation substrates 101 and 102. The discharge gas space 108 is filled with discharge gas of helium, neon, or xenon, or gas mixture thereof.
By referring back to FIG. 1, in the display panel 1, n (where n is a natural number) scan electrodes 31 to 3n (103) and n sustain electrodes 41 to 4n (104) are alternately provided at established intervals. These scan electrodes 31 to 3n and sustain electrodes 41 to 4n are all extending in the line direction (horizontal direction). The display panel 1 also includes m (where m is a natural number) data electrodes 101 to 10m (107) extending in the column direction (vertical direction). These data electrodes 101 to 10m are so placed as to be orthogonal to the scan electrodes 31 to 3n and the sustain electrodes 41 to 4n when viewed from the top. Display cells are also provided in a matrix, each at a point most proximal to both the scan electrode and the data electrode, or at a point most proximal to both the sustain electrode and the data electrode. This means that the display panel 1 carries (n×m) display cells.
The plasma display device is provided with a drive power source 21, a controller 22, a scan driver 23, a scan pulse driver 24, a sustain driver 25, and a data driver 26, all serve as drive circuits of the display panel 1.
The drive power source 21 generates, for example, a logic voltage Vdd of 5V, a data voltage Vd of about 70V, and a sustain voltage Vs of about 170V. The drive power source 21 also generates, based on the sustain voltage Vs, a priming voltage Vp of about 400V, a scan base voltage VbW of about 100V, and a bias voltage Vsw of about 180V. The logic voltage Vdd goes to the controller 22, the data voltage Vd goes to the data driver 26, the sustain voltage Vs goes to both the scan driver 23 and the sustain driver 25, the priming voltage Vp and the scan base voltage Vbw go to the scan driver 23, and the bias voltage Vsw goes to the sustain driver 25.
The controller 22 is a circuit for generating various control signals based on a video signal Sv coming from the outside. The control signals include scan driver control signals Sscd1 to Sscd6, scan pulse driver control signals Sspd11 to Sspd1n and Sspd21 to Sspd2n, sustain driver control signals Ssud1 to Ssud3, and data driver control signals Sdd11 to Sdd1m and Sdd21 to Sdd2m. The scan driver control signals Sscd1 to Sscd6 all go to the scan driver 23, the scan pulse driver control signals Sspd11 to Sspd1n and Sspd21 to Sspd2n all go to the scan pulse driver 24, the sustain driver control signals Ssud1 to Ssud3 all go to the sustain driver 25, and the data driver control signals Sdd11 to Sdd1m and Sdd21 to Sdd2m all go to the data driver 26.
Referring to FIG. 2, the scan driver 23 is exemplarily configured by six switches 231 to 236. The switch 231 receives the priming voltage Vp at one end, and the other end thereof is connected to a positive line 27. The switch 232 receives the sustain voltage Vs at one end, and the other end thereof is connected also to the positive line 27. The switch 233 is grounded at one end, and the other end thereof is connected to a negative line 28. The switch 234 receives the scan base voltage Vbw at one end, and the other end thereof is connected also to the negative line 28. The switch 235 is grounded at one end, and the other end thereof is connected to the positive line 27. The switch 236 is grounded at one end, and the other end thereof is connected to the negative line 28. These switches 231 to 236 are respectively turned ON or OFF based on their corresponding scan driver control signals Sscd1 to Sscd6. The voltage of a predetermined waveform is then forwarded to the scan pulse driver 24 through the positive and negative lines 27 and 28. In the scan driver 23, a resistance element (not shown) such as a field-effect transistor is connected to between the switch 231 and a node (not shown) receiving the priming voltage Vp, and the switch 232 and a node (not shown) receiving the sustain voltage Vs. Such a resistance element successively changes the voltage for application to the switches 231 and 232 through change of the resistance value between source and drain as a result of application of control voltage to a gate.
Still referring to FIG. 2, the scan pulse driver 24 is exemplarily configured by n switches 2411 to 241n, n switches 2421 to 242n, n diodes 2431 to 243n, and n diodes 2441 to 244n. The diodes 2431 to 243n are connected in parallel to their corresponding switches 2411 to 241n at both ends, and the diodes 2441 to 244n are connected in parallel to their corresponding switches 2421 to 242n at both ends. The switches 241a (where a is a natural number equal to or smaller than n) is connected serially to the switch 242a. The switches 2411 to 241n are each connected to the negative line 28 at one end, and the switches 2421 to 242n are each connected to the positive line 27 at one end. The connection point between the switches 241a and 242a is connected to the scan electrode 3a that is placed at the ath line, counting from the upper side of the display panel 1. The switches 2411 to 241n, and 2421 to 242n are each turned ON or OFF based on the scan pulse driver control signals Sspd11 to Sspd1n and Sspd21 to Sspd2n. The scan electrodes 31 to 3n then sequentially receive the voltage Psc1 to Pscn of a predetermined waveform.
By referring to FIG. 3, the sustain driver 25 is exemplarily configured by three switches 251 to 253. The switch 251 receives the sustain voltage Vs at one end, and the other end thereof is connected to all the sustain electrodes 41 to 4n. The switch 252 is grounded at one end, and the other end thereof is connected to all the sustain electrodes 41 to 4n. The switch 253 receives the bias voltage Vsw at one end, and the other end thereof is connected to all the sustain electrodes 41 to 4n. The switches 251 to 253 are each turned ON or OFF based on their corresponding sustain driver control signals Ssud1 to Ssud3. The sustain electrodes 41 to 4n then simultaneously receive a voltage Psu of a predetermined waveform.
By referring to FIG. 4, the data driver 26 is exemplarily configured by m switches 2611 to 261m, m switches 2621 to 262m, m diodes 2631 to 263m, and m diodes 2641 to 264m. The diodes 2631 to 263m are connected in parallel to their corresponding switches 2611 to 261m at both ends, and the diodes 2641 to 264m are connected in parallel to their corresponding switches 2621 to 262m at both ends. The switches 261b (where b is a natural number equal to or smaller than m) is connected serially to the switch 262b. The switches 2611 to 261m are each grounded at one end, and the switches 2621 to 262m each receive the data voltage Vd at one end. The connection point between the switches 261b to 262b is connected to the data electrode 10b at the bth line, counting from the left side of the display panel 1. The switches 2611 to 261m, and 2621 to 262m are each turned ON or OFF based on the data driver control signals Sdd1m to Sdd21 and Sdd21 to Sdd2m. The data electrodes 101 to 10m then sequentially receive the voltages Pd1 to Pdm of a predetermined waveform.
Described next is the write-select drive operation of the conventional plasma display device structured as above. FIG. 6 is a timing chart showing the write-select drive operation of the conventional plasma display device. In the drive method of the conventional plasma display device, a field is configured by a plurality of subfields (hereinafter, referred also to as SFs), and each subfield has four periods of priming period Tp, address period Ta, sustain period Ts, and charge removal period Te, those of which are set in sequence. In the priming period Tp, the display cells are all illuminated so as to activate, equalize, and initiate their charge state. In the address period Ta, the display cells are all made to cause write discharge to generate wall charge before generating sustain discharge in the subsequent sustain period Ts. In the sustain period Ts, the sustain discharge is generated in the display cells formed with the wall charge in the preceding address period Ta. In the charge removal period Te, the wall charge is removed from the display cells illuminated in the sustain period Ts.
Described next in detail is the operation in each of those periods. In the below, as to the scan electrodes and the sustain electrodes, their reference potential is the sustain voltage Vs. The potential higher than the sustain voltage Vs is referred to as positive potential, and as negative potential for the lower potential. The reference potential of the data electrodes is a ground voltage GND, and the potential higher than that is referred to as positive potential, and as negative potential for the lower potential.
In the priming period Tp, the controller 22 first starts generating control signals, i.e., the scan driver control signals Sscd1 to Sscd6, the sustain driver control signals Ssud1 to Ssud3, and the scan pulse driver control signals Sspd11 to Sspd1n and Sspd21 to Sspd2n. The control signals also include the data driver control signals Sdd11 to Sdd1m in the level based on the video signal Sv coming from the outside, and the data driver control signals Sdd21 to Sdd2m in the low level. Thus generated control signals are forwarded to their corresponding drivers.
As a result, in the priming period Tp, the high-level scan driver control signal Sscd1 turns ON the switch 231, and the high-level sustain driver control signal Ssud2 turns ON the switch 252. The scan pulse driver control signal Sspd11 to Sspd1n are all lowered in level so that the switches 2411 to 241n are all turned OFF, and the scan pulse driver control signals Sspd21 to Sspd2n are all raised in level so that the switches 2421 to 242n are all turned ON. Accordingly, as shown in FIG. 6, the scan electrodes 31 to 3n all receive a positive priming pulse Pprp, and the sustain electrodes 41 to 4n all receive a negative priming pulse Pprn. In the display cells, this causes priming discharge in the discharge gas space 108 in the vicinity of an electrode-to-electrode gap, i.e., between the scan electrodes 103 (31 to 3n) and the sustain electrodes 104 (41 to 4n). At this time, by successively changing the resistance value of the resistance element that is connected between the switch 231 and the priming voltage Vp, the priming pulse Pprp can be of a saw tooth waveform with which the potential continuously increases from the sustain voltage Vs to the priming voltage Vp.
In this manner, active particles are generated in the discharge space 108 for helping generate write discharge in the display cells. Moreover, the scan electrodes 31 to 3n are each attached with the negative wall charge, the sustain electrodes 41 to 4n are each attached with the positive wall charge, and the data electrodes 101 to 10m are each attached with the positive wall charge thereon.
Thereafter, responding to the sustain driver control signal Ssud2 lowered in level, the switch 252 is responsively turned OFF, and the sustain electrodes 104 (41 to 4n) are put into the floating state. As a result, the potential of the sustain electrodes 104 is successively increased due to the potential of the scan electrodes 103, thereby stopping the priming discharge. As such, stopping the priming discharge with the sustain electrodes 104 put into the floating state can prevent the priming discharge from being excessive, favorably reducing the black level, i.e., the brightness of the lowest tone (number 0). Accordingly, to reduce such a black level, preferably, the sooner the better to put the sustain electrodes 104 into the floating state as long as the priming discharge can sufficiently occur.
The sustain driver control signal Ssud1 is then raised in level, and the switch 251 is responsively turned ON. The scan driver control signal Sscd2 is then lowered in level, and the switch 232 is turned OFF. The scan driver control signal Sscd3 is then raised in level, and the switch 233 is turned ON. As a result, after the sustain electrodes 41 to 4n are all maintained at the potential of 170V sustain voltage Vs, the scan electrodes 31 to 3n each receive a priming removal pulse Ppre. Such pulse application resultantly causes weak-level discharge in every display cell, and this reduces the wall charge on the electrodes, i.e., the negative wall charge on the scan electrodes 31 to 3n, the positive wall charge on the sustain electrodes 41 to 4n, and the positive wall charge on the data electrodes 101 to 10m.
In the early address period Ta, the switch 253 is being ON due to the high-level sustain driver control signal Ssud3, and the switches 234 and 235 are both being ON due to the high-level scan driver control signals Sscd4 and Sscd5, both are those provided in the later priming period Tp. Here, the switches 2411 to 241n are being ON, and the switches 2421 to 242n are being OFF due to the high-level scan pulse driver control signals Sspd11 to Sspd1n, and the low-level scan pulse driver control signals Sspd21 to Sspd2n. Therefore, the sustain electrodes 41 to 4n each receive a positive-going (bias voltage VsW) bias pulse Pbp, and the potential of the pulses Psc1 to Spcn to be applied to the scan electrodes 31 to 3n is temporarily maintained at the scan base voltage Vbw.
Under such a state, the scan pulse driver control signals Sspd11 to Sspd1n are sequentially lowered in level, and correspondingly thereto, the scan pulse driver control signals Sspd21 to Sspd2n are sequentially raised in level. In response to such level change, the switches 2411 to 241n are consecutively turned OFF, and the switches 2421 to 242n are consecutively turned ON. In synchronization therewith, although not shown, the data driver control signals Sdd11 to Sdd1m are raised in level based on the video signal Sv, and correspondingly thereto, the data driver control signals Sdd21 to Sdd2m are lowered in level. In response, the switches 2611 to 261m are all turned ON based on the video signal Sv, and the switches 2621 to 262m are all turned OFF. When writing is performed in the display cell locating at the ath line and the bth column, the scan electrode 3a at the ath line receives the negative scan pulse Pwsn, and the data electrode 10b at the bth column receives the positive data pulse Pdb. This resultantly causes opposing discharge in the display cell at the ath line and the bth column. This opposing discharge serves as a trigger, and surface discharge occurs as writing discharge between the scan electrodes and the sustain electrodes, whereby the electrodes are attached with the wall charge. The display cells having no writing discharge caused therein remain in the less-wall-discharge state after the electric charge is removed in the priming period Ta.
In the next sustain period Ts, the scan driver control signals Sscd2 and Sscd6 alternately rise and fall repeatedly for the number of times predetermined for the subfield. As a result, the switches 232 and 236 are alternately turned ON and OFF repeatedly. In synchronization therewith, the sustain driver control signals Ssud1 and Ssud2 alternately rise and fall repeatedly for the number of times predetermined for the subfield, and resultantly the switches 251 and 252 are alternately turned ON and OFF repeatedly. Accordingly, the scan electrode 31 to 3n each receive the negative sustain pulse Psun1 for the number of times predetermined for the subfield, and in synchronization with the sustain pulse Psun1, the sustain electrodes 41 to 4n receive the negative sustain pulse Psun2 for the number of times predetermined for the subfield. At this time, the display cells having no writing performed therein in the address period Ta have considerably less amount of wall charge, and thus no sustain discharge occurs even if the display cells receive the sustain pulse. On the other hand, in the display cells having writing discharge caused therein in the address period Ta, the scan electrodes are attached with the positive charge, and the sustain electrodes are attached with the negative charge. The sustain pulse and the wall charge voltage are thus superposed on each other, and the voltage between the electrodes exceeds the discharge start voltage so that discharge occurs.
In the next charge removal period Te, the scan driver control signal Sscd3 rises, and thus the switch 233 is accordingly turned on. As a result, the scan electrodes 31 to 3n each receive a negative charge removal pulse Peen. Such pulse application resultantly causes weak-level discharge in every display cell, and this reduces the wall charge on the scan electrodes and sustain electrodes in the display cells that have been illuminated in the sustain period Ts, whereby the display cells can be all made uniform in their charge state.
With such a conventional technology, however, there are the following problems. The discharge start voltage at which discharge starts in the display cells is not generally constant but varies. With Paschen's Law, the discharge start voltage is dependent on the product of the electrode-to-electrode distance and the display cell pressure. Under the requirements for the plasma display devices to operate, the discharge start voltage will be higher with the larger product. If the PDP is increased in temperature, for example, the pressure increase is observed not only for the discharge gas itself but also in the discharge cells. This is due to gas escape, which is absorbed in the partition walls in the display cells. This resultantly increases the discharge start voltage. If no discharge occurs for a long time, charged particles in the discharge cells are reduced in number with time. This is the reason why the discharge start voltage is higher at start-up of the plasma display devices compared with during their steady-state operation.
FIG. 7 is a timing chart showing in detail the priming period Tp of FIG. 6. FIG. 7 shows a part of the address period Ta subsequent to the priming period Tp, and the charge removal period Te for the preceding subfield. As shown in FIG. 7, when the discharge start voltage takes a normal value, e.g., when the PDP is at the normal temperature, the priming discharge starts at a time t1 at which the potential difference (hereinafter, referred also to as surface voltage) between the scan electrodes and the sustain electrodes exceeds the discharge start voltage. At a time t3 at which the sustain electrodes are put into the floating state, the priming discharge stops. On the other hand, when the discharge start voltage takes a higher value than usual, i.e., when the PDP is at the high temperature, the surface voltage exceeds the discharge start voltage at a time t2 later than the time t1 so that the priming discharge starts. The priming discharge started as such stops at the time t3. Therefore, when the PDP is high in temperature, the priming discharge does not continue that long compared with when the PDP is at the normal temperature, and thus the priming discharge is not enough. If the discharge start voltage is considerably high, the surface voltage may not reach the discharge start voltage even at the time t3, and thus no priming discharge may occur.
In consideration thereof, to cause the priming discharge without fail even when the discharge start voltage is high, there is no choice but to set the priming voltage Vp higher. Thus set priming voltage Vp is unnecessarily high for the normal conditions with the low discharge start voltage, resultantly causing the priming discharge to be excessive. The resulting excessive priming discharge raises the black level, thereby lowering the image contrast. If the priming voltage Vp is set at its optimum value for the normal conditions with the low discharge start voltage, as described above, no priming discharge occurs when the discharge start voltage is high. Even if the priming discharge occurs, the resulting level is not enough. This results in writing failure for some display cells with no writing discharge occurred. In the display cells observed with such writing failure, no sustain discharge occurs, and thus images suffer from inconsistency, unfavorably degrading in image quality.
For betterment, Patent Document 1 (JP-A-2000-20021) describes the technology of increasing the priming voltage at start-up of plasma display devices compared with during their steady-state operation with rectangular priming pulses. In Patent Document 1, there is a description telling that the priming discharge occurs without fail even at the PDP start-up.
In the technology of Patent Document 1, however, the rectangular priming pulses arises a problem. That is, the rectangular pulses cause instability during discharge, and the resulting discharge will be unnecessarily too bright. In this sense, the rectangular priming pulses are not considered practical.
In view thereof, there is a possibility of increasing the priming voltage only at the PDP start-up as described in Patent Document 1 with the saw tooth priming pulses as shown in FIGS. 13 and 14. With this method, the priming discharge can be indeed started when the discharge start voltage is high, but the start time therefor varies. The concern here is that the time t3 at which discharge stops is substantially constant irrespective of the discharge start voltage. Therefore, a change of the discharge start voltage leads to a length change of the period for the priming discharge, causing the priming discharge to be nonuniform. As a result, the display cells through with the priming period will not be uniform in their charge state depending on the operation requirements, resulting in varying display quality.